1. Field of the Invention
The present invention relates to a system and a protocol for digital communications, and more particularly, to a system and a protocol for asymmetrical digital subscriber line (ADSL) interfaces.
2. Background
The telecommunications industry has developed schemes for transmitting telephony signals in digital formats, for example, in the form of time division multiplexed (TDM) signals for transmission over a physical layer interface, such as a conventional subscriber bus interface (SBI). Transmission over a conventional SBI is typically achieved by using an industry-standard framed format in which digital communications payload data are assigned to a plurality of SBI frames each having a duration of 125 xcexcs. Each of the SBI frames is divided into 32 SBI time slots for carrying communications payload data in a conventional type of digitized telephone service. An example of a conventional telephone service is a plain old telephone service (POTS), which uses an industry-standard digital format known to a person skilled in the art.
A large number of conventional channel banks have been deployed to support conventional narrowband telephony traffic such as POTS traffic. In a conventional channel bank for supporting narrowband POTS traffic, a conventional narrowband channel bank control unit (BCU) is connected to a plurality of conventional POTS line cards to transfer digitized telephony signals in a conventional industry-standard SBI frame format, wherein each of the SBI frames consists of 32 SBI time slots each having a duration of 3.90625 xcexcs.
In a typical channel bank configuration, a conventional standard channel bank backplane is provided with a plurality of metallic backplane traces which are connected between the conventional BCU and he conventional POTS line cards for the transmission of narrowband POTS traffic. The channel bank backplane is typically installed on the back of a standard equipment rack which is capable of accepting the conventional BCU and the conventional POTS line cards. A plurality of standard line card slots are provided on a typical channel bank backplane to accept the conventional POTS line cards. The capacity of the channel bank can be flexibly increased or decreased by plugging conventional POTS line cards into or out of the line card slots on the channel bank backplane.
It is desirable that high speed broadband data communications traffic be supported in existing channel banks which are already widely deployed. More specifically, it is desirable that asymmetrical digital subscriber line (ADSL) traffic be supported on existing channel bank backplanes to take advantage of the large number of channel banks already deployed. Furthermore, it is desirable that a new high speed downstream cell bus interface protocol and system be provided for ADSL traffic with increased speed, efficiency and data integrity while taking advantage of existing channel banks already deployed in conventional telephone switching networks.
The present invention provides an asymmetrical digital subscriber line (ADSL) downstream high speed cell bus interface protocol and a system for the downstream transmission of ADSL traffic with improved speed, efficiency and data integrity. In accordance with the present invention, a method of data transmission roughly comprises the steps of:
(a) synchronizing frame boundaries of an asymmetrical digital subscriber line (ADSL) frame by using a subscriber bus interface (SBI) frame consisting of a predetermined number of SBI time slots;
(b) assigning a plurality of cell packets to the ADSL frame, the number of cell packets in the ADSL frame different from the number of SBI time slots in the SBI frame; and
(c) providing an internal cell for transmission within one of the cell packets, the internal cell comprising a plurality of routing tag bytes and a plurality of payload bytes.
In an embodiment, the internal cell further comprises a plurality of header bytes. In an embodiment, the internal cell in each of the cell packets is encoded to generate an encoded internal cell. In a further embodiment, convolutional forward error correction (FEC) encoding is applied to the internal cell to generate the encoded internal cell. The encoded internal cell is assigned to one of the cell packets in the ADSL frame for downstream transmission.
In an embodiment, the cell packets in an ADSL frame are transmitted downstream from an ADSL bank control unit (ABCU) to a plurality of ADSL line units. In a further embodiment, the routing tag bytes in each of the cell packets comprise a first routing tag byte and a second routing tag byte. In an embodiment, the first routing tag byte comprises a plurality of card slot bits to designate a card slot number for a selected one of the ADSL line units to which the cell packet is to be transmitted.
In an embodiment, each of the ADSL line units has a plurality of destination ports to which the cell packet is capable of being transmitted downstream. In a further embodiment, the second routing tag byte comprises a plurality of cell type indicator bits to indicate to the selected ADSL line unit at least one of the destination ports to which the cell packet is to be transmitted further downstream.
In an embodiment, the ABCU is connected to the ADSL line units through a plurality of data buses each comprising a plurality of data lines and a clock line. In a further embodiment, the first routing tag byte further comprises a version indicator bit capable of indicating whether only one cell packet is transmitted from the ABCU to the ADSL line units through all of the data buses at a time or different cell packets are transmitted simultaneously from the ABCU to the ADSL line units through different data buses, respectively. In another embodiment, the version indicator bit is capable of indicating the format in which the routing tag bytes are implemented.
In an embodiment, the first routing tag byte further comprises a reserved bit temporally preceding the card slot bits. In a further embodiment, the version indicator bit temporally precedes the reserved bit in the first routing tag byte.
In an embodiment, the cell type indicator bits are capable of indicating one of the destination ports as a unicast destination selected for the downstream transmission of the cell packet from the ADSL line unit. In a further embodiment, the cell packet is transmitted to the selected unicast destination via a respective downstream queue based upon the cell type indicator bits.
In a further embodiment, the cell type indicator bits are further capable of indicating one of a plurality of multicast groups selected for the downstream transmission of the cell packet from the ADSL line unit, each of the multicast groups consisting of more than one of the destination ports. In yet a further embodiment, the cell packet is transmitted to the destination ports in the selected multicast group via a plurality of respective downstream queues based upon the cell type indicator bits.
In a further embodiment, the cell type indicator bits are further capable of carrying an idle cell indicator to signify to the selected ADSL line unit that the cell packet is to be discarded. In a further embodiment, the cell type indicator bits are further capable of carrying a central processing unit (CPU) cell indicator to signify to the selected ADSL line unit that the cell packet is to be transmitted via a cell bus data link(CBDL) downstream queue.
In a further embodiment, the cell type indicator bits are further capable of carrying a loop back cell indicator to signify to the selected ADSL line unit that the cell packet is to be transmitted in a loop back queue from the selected ADSL line unit to the ABCU. In an embodiment, the second routing tag byte further comprises a plurality of reserved bits temporally preceding the cell type indicator bits.
In an embodiment, data bits in each of the cell packets which are transmitted downstream from the ABCU to the ADSL line units are referenced by a clock signal having rising and falling edges with a 50% duty cycle. In an embodiment, the data bits are transmitted on both the rising and falling edges of the clock signal, thereby producing a data rate which is twice the clock frequency for downstream transmission of the data bits. In a further embodiment, the data bits are transmitted with a phase shift of 90xc2x0 with respect to the clock signal.
In an embodiment in which the encoded internal cell does not have a sufficient bit length to occupy a cell packet completely, unused bits are padded after the encoded internal cell to fill up the cell packet. In an embodiment in which the total length of the cell packets assigned to an ADSL frame is not sufficient to occupy the ADSL frame completely, unused bytes are padded after the cell packets to fill up the ADSL frame. In an embodiment in which the internal cell in each cell packet is encoded, the unused bits are not encoded.
In accordance with the present invention, a communications system for downstream transmission of data roughly comprises:
(a) an asymmetrical digital subscriber line (ADSL) bank control unit (ABCU) comprising a plurality of cell buses;
(b) a plurality of sets of data lines and a plurality of clock lines connected to the cell buses; and
(c) a plurality of ADSL line units arranged in a plurality of rows, the ADSL line units in each row connected to a respective one of the cell buses through a respective one of the sets of data lines and a respective one of the clock lines,
wherein data bits are transmitted within a plurality of internal cells in a plurality of cell packets in an ADSL frame through the data lines from the ABCU to the ADSL line units,
wherein a clock signal is provided through each of the clock lines,
wherein frame boundaries of the ADSL frame are synchronized by using a subscriber bus interface (SBI) frame consisting of a predetermined number of SBI time slots, the number of cell packets in the ADSL frame different from the number of SBI time slots in the SBI frame, and
wherein each of the internal cells comprises a plurality of routing tag bytes, a plurality of header bytes, and a plurality of payload bytes.
In an embodiment, each of the ADSL line units comprises a plurality of destination ports, and the routing tag bytes in each of the internal cells comprise a first routing tag byte and a second routing tag byte. In an embodiment, the first routing tag byte comprises a plurality of card slot bits to designate a card slot number for a selected one of the ADSL line units to which the cell packet is to be transmitted from the ABCU. In a further embodiment, the first routing tag byte further comprises a version indicator bit capable of indicating whether only one cell packet is transmitted from the ABCU to the ADSL line units through all of the cell buses at a time or different cell packets are transmitted simultaneously from the ABCU to different rows of ADSL line units through different cell buses, respectively.
In an embodiment, the second routing tag byte comprises a plurality of cell type indicator bits. In an embodiment, each of the ADSL line units further comprises a router to direct the cell packet to at least one of the destination ports based upon the cell type indicator bits. In an embodiment, the cell type indicator bits are capable of indicating a selected one of the destination ports as a unicast destination for the cell packet. In a further embodiment, the router in the ADSL line unit directs the cell packet to the selected unicast destination port based upon the cell type indicator bits.
In an embodiment, a plurality of multicast groups are provided to include different combinations of downstream destinations. In a further embodiment, the cell type indicator bits are further capable of indicating a selected one of the multicast groups for the downstream transmission of the cell packet. Each of the multicast groups consists of more than one of the destination ports. In this embodiment, the router is capable of directing the cell packet to the destination ports in the selected multicast group based upon the cell type indicator bits.
In an embodiment, the cell buses for transmitting the data bits downstream from the ABCU to the ADSL line units comprise high speed cell buses (HSCBs). In a further embodiment, the system further comprises an additional ABCU having a plurality of cell buses each connected to a respective row of ADSL line units to provide redundancy and fault protection for downstream transmission of the cell packets.
Advantageously, the ADSL downstream high speed cell bus interface protocol according to the present invention allows an existing channel bank backplane to support broadband ADSL traffic by implementing at least one ABCU in a conventional channel bank and plugging a plurality of broadband ADSL line units into existing line card slots on the channel bank backplane. Furthermore, data integrity on the channel bank backplane can be enhanced by encoding the internal cells in the cell packets of an ADSL frame in an embodiment according to the present invention.
Furthermore, in an embodiment in which the data bits are transmitted on both the rising and falling edges of a clock signal with a phase shift, signal frequency over the backplane traces along which the data lines and the clock lines run between the ABCU and the ADSL line units can be reduced. A cleaner clock signal can be provided to the ADSL line units because the clock frequency is lower than the data rate. Furthermore, in an embodiment in which the frame boundaries of the ADSL frame is derived from a standard SBI frame, frame synchronization can be achieved with reduced design complexity.
Furthermore, in an embodiment in which each of the cell packets comprises a plurality of routing tag bytes, a plurality of card slot bits are provided to designate a selected ADSL line unit for receiving the cell packet, and a plurality of cell type indicator bits are provided for further downstream transmission of the cell packet from the selected ADSL line unit. In an embodiment, a version indicator bit is provided in one of the routing tag bytes to indicate the format in which the routing tag bytes are implemented.